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Comparison Overview

Loro PianaLoro Piana
VS
RichemontRichemont
Loro Piana

Loro Piana

Via della Moscova, 33, Milan, Lombardy, 20121, IT

Last Update: 28/03/2026

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Between 750 and 799
https://www.loropiana.com
781/1000Fair

Loro Piana operates in the luxury goods industry making uncompromised quality its mission and offering a complete selection of ready-to-wear, accessories and gifts made in Italy with the finest raw materials. It reaches its customers through a global retail network, on ...

NAICS:4483
NAICS Definition:Jewelry, Luggage, and Leather Goods Stores
Employees:3,127
Subsidiaries:1
12-month incidents
0
Known data breaches
0
Attack type number
0
Richemont

Richemont

Chemin de la Chênaie 50, Bellevue, Geneva, CH, 1293

Last Update: 03/04/2026

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Between 800 and 849
http://www.richemont.com/
834/1000Good

At Richemont, we craft the future. Our unique portfolio includes prestigious Maisons distinguished by their craftsmanship and creativity. Richemont’s ambition is to nurture its Maisons and businesses and enable them to grow and prosper in a responsible, sustainable mann...

NAICS:4483
NAICS Definition:Jewelry, Luggage, and Leather Goods Stores
Employees:30,756
Subsidiaries:5
12-month incidents
0
Known data breaches
0
Attack type number
0

Compliance Ranges Comparison

Based On Specific Ai Models Category
Loro Piana

Loro Piana

-
ISO 27001Not verified
ISO 27001
-
SOC2 Type 1Not verified
SOC2 Type 1
-
SOC2 Type 2Not verified
SOC2 Type 2
-
GDPRNot verified
GDPR
-
PCI DSSNot verified
PCI DSS
-
HIPAANot verified
HIPAA
Richemont

Richemont

-
ISO 27001Not verified
ISO 27001
-
SOC2 Type 1Not verified
SOC2 Type 1
-
SOC2 Type 2Not verified
SOC2 Type 2
-
GDPRNot verified
GDPR
-
PCI DSSNot verified
PCI DSS
-
HIPAANot verified
HIPAA

Benchmark & Cyber Underwriting Signals

Incidents vs Retail Luxury Goods and Jewelry Industry Avg (This Year)

No incidents recorded for Loro Piana in 2026.

Incidents

Incidents vs Retail Luxury Goods and Jewelry Industry Avg (This Year)

No incidents recorded for Richemont in 2026.

Incidents

Incident History - Loro Piana (X = Date, Y = Severity)

Loro Piana cyber incidents detection timeline including parent company and subsidiaries.

R - Ransomware
C - Cyber Attack
D - Data Breach
V - Vulnerability

Incident History - Richemont (X = Date, Y = Severity)

Richemont cyber incidents detection timeline including parent company and subsidiaries.

No timeline data available
R - Ransomware
C - Cyber Attack
D - Data Breach
V - Vulnerability

Notable Incidents

Last Cyber / HR Incidents / Global...
Loro Piana

Loro Piana

Incidents
No explicit notable incidents reported.
Richemont

Richemont

Incidents
No explicit notable incidents reported.

FAQ

Between Loro Piana company and Richemont company, which one has the best AI Cybersecurity Score ?
Between Loro Piana company and Richemont company, which one has experienced more cyber incidents in the past ?
Between Loro Piana company and Richemont company, which one has experienced more cyber incidents this year ?
Between Loro Piana company and Richemont company, which one has experienced at least one ransomware attack ?
Between Loro Piana company and Richemont company, which one has experienced at least one data breach ?
Between Loro Piana company and Richemont company, which one has experienced at least one targeted cyberattack ?
Between Loro Piana company and Richemont company, which one has experienced at least one vulnerability ?
Between Loro Piana company and Richemont company, which one holds the most compliance certifications ?
Between Loro Piana company and Richemont company, which one holds the fewest compliance certifications ?
Between Loro Piana company and Richemont company, which one has the most subsidiaries ?
Between Loro Piana company and Richemont company, which one has the largest number of employees ?
Between Loro Piana and Richemont, which company holds both SOC 2 Type 1 certifications ?
Between Loro Piana and Richemont, which company holds both SOC 2 Type 2 certifications ?
Which company is ISO 27001 certified - Loro Piana or Richemont ?
Which company is PCI DSS compliant - Loro Piana or Richemont ?
Between Loro Piana and Richemont, which company complies with HIPAA regulations for healthcare data ?
Between Loro Piana and Richemont, which company complies with GDPR requirements ?

Latest Global CVEs

CVE-2026-78122
SUMMARY

docker-socket-proxy fails to properly gate read endpoints in the /containers Docker API namespace when the CONTAINERS environment variable is set. Attackers can use GET requests to /containers/{id}/archive, /containers/{id}/export, /containers/{id}/logs, and /containers/{id}/top to read arbitrary files and download entire container filesystems as tar archives.

PUBLISHED
Date2026-08-22
UPDATED
Date2026-08-22
RISK INFORMATION (Score: 7.4)
CVSS3
Base Score: 7.4
Complexity: LOW
CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:C/C:H/I:N/A:N
CVSS4
Base Score: 8.3
Complexity: LOW
CVSS:4.0/AV:A/AC:L/AT:N/PR:N/UI:N/VC:H/VI:N/VA:N/SC:H/SI:N/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X
IMPACT SCORE
4
EXPLOITABILITY
2.8
CVE-2026-78049
SUMMARY

A vulnerability has been found in Systerel S2OPC up to 1.7.3. Impacted is the function SOPC_NodeMgtHelperInternal_AddVariableNodeAttributes of the file src/ClientServer/address_space/internal/sopc_node_mgt_helper_internal.c of the component AddNodes Service. The manipulation of the argument UserAccessLevel leads to out-of-bounds read. It is possible to initiate the attack remotely. A high degree of complexity is needed for the attack. The exploitability is considered difficult. The exploit has been disclosed to the public and may be used. The identifier of the patch is aafbd37d381b618312ebdf5ddf57027f62c14fdd. It is suggested to install a patch to address this issue.

PUBLISHED
Date2026-08-22
UPDATED
Date2026-08-22
RISK INFORMATION (Score: 3.7)
CVSS2
Base Score: 2.6
Complexity: HIGH
AV:N/AC:H/Au:N/C:N/I:N/A:P
CVSS3
Base Score: 3.7
Complexity: HIGH
CVSS:3.1/AV:N/AC:H/PR:N/UI:N/S:U/C:N/I:N/A:L
CVSS4
Base Score: 2.9
Complexity: HIGH
CVSS:4.0/AV:N/AC:H/AT:N/PR:N/UI:N/VC:N/VI:N/VA:L/SC:N/SI:N/SA:N/E:P/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X
IMPACT SCORE
1.4
EXPLOITABILITY
2.2
CVE-2026-12999
SUMMARY

The Infineon Airoc Wi-Fi driver's transmit callback airoc_mgmt_send() in drivers/wifi/infineon/airoc_wifi.c allocates a net_buf from the fixed airoc_pool for every outbound packet. When whd_network_send_ethernet_data() returns a synchronous failure, the underlying WHD library does not take ownership of the buffer, but the pre-fix driver returned -EIO without releasing it. Each failed transmit therefore permanently leaks one buffer from the pool. airoc_pool is small and fixed (AIROC_WIFI_TX_PACKET_POOL_COUNT + AIROC_WIFI_RX_PACKET_POOL_COUNT, default 20 buffers) and is shared by WHD's whd_host_buffer_get callback for both transmit and receive. Once enough send failures have leaked the pool dry, airoc_wifi_host_buffer_get() returns WHD_BUFFER_ALLOC_FAIL for all subsequent allocations, so both transmit and the WHD-driven receive path fail and Wi-Fi connectivity is lost until the device is rebooted. The leak occurs only on the transmit error path. A Wi-Fi-adjacent attacker can influence the conditions that cause synchronous send failures (for example by deauthenticating/disassociating the station while the local stack continues to attempt transmits), and ordinary transient failures over the device's lifetime accumulate toward the same state. Reliable on-demand triggering is of high complexity and the impact is availability-only, but the resulting denial of service is permanent and non-recoverable without a reboot. The fix releases the buffer with airoc_wifi_buffer_release() on the failure branch, returning it to the pool. The commit also removes a redundant k_sem_give() in airoc_mgmt_disconnect(); because data->sema_common is a binary semaphore (limit 1) the duplicate give merely saturated at 1 and had no security impact.

PUBLISHED
Date2026-08-22
UPDATED
Date2026-08-22
RISK INFORMATION (Score: 5.3)
CVSS3
Base Score: 5.3
Complexity: HIGH
CVSS:3.1/AV:A/AC:H/PR:N/UI:N/S:U/C:N/I:N/A:H
IMPACT SCORE
3.6
EXPLOITABILITY
1.6
CVE-2026-74733
SUMMARY

In the Linux kernel, the following vulnerability has been resolved: gpio: pca953x: fix pca953x_irq_bus_sync_unlock regmap lock Locking is disabled in the regmap config as this driver uses its own lock. This means that all calls to regmap functions (read or write) must hold the i2c_lock. The function pca953x_irq_bus_sync_unlock() did not do this, and it was therefore possible that multiple threads could cause an incorrect register to be read/written. A previous patch partly fixed this, but only protected the write to the interrupt mask register, and not the read from the direction register.

PUBLISHED
Date2026-08-22
UPDATED
Date2026-08-22
IMPACT SCORE
NA
EXPLOITABILITY
NA
CVE-2026-74732
SUMMARY

In the Linux kernel, the following vulnerability has been resolved: drm/amd/display: Check for tg ops in dce110_set_avmute Some older DCE timing generators do not implement is_tg_enabled in their ops table. Calling it unconditionally when waiting for AV mute frames causes a NULL pointer dereference on Southern Islands dGPUs when turning the display off over HDMI. Check that tg and the required ops exist before waiting for frames. (cherry picked from commit 2686a0c0aaa07bec2e24131835cf27b5fd4935a5)

PUBLISHED
Date2026-08-22
UPDATED
Date2026-08-22
IMPACT SCORE
NA
EXPLOITABILITY
NA